Low Power Design for DVFS Capable Software
10th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference, UEMCON 2019, New York, United States Of America, 10 - 12 October 2019, pp.1175-1179, (Full Text)
- Publication Type: Conference Paper / Full Text
- Doi Number: 10.1109/uemcon47517.2019.8993027
- City: New York
- Country: United States Of America
- Page Numbers: pp.1175-1179
- Keywords: DVFS, low power, off-line algorithms, power profile
- Istanbul University Affiliated: No
Abstract
Today's central processing unit (CPU) technology makes it possible for a processor to adjust its voltage and clock frequency dynamically depending on its current CPU load, memory load, or operating system requests. Higher energy saving is possible if the application's power profile can be estimated or determined fast and accurate. If the application's power profile is completely known prior to execution, then maximum/optimum power saving is possible using off-line dynamic voltage and frequency scaling (DVFS) algorithms. The question is, how to determine full power-profile of an application prior to execution and how much power saving is possible. In this paper, we discuss the methodology to determine full power profile of an application and calculate potential energy savings using off-line DVFS algorithms for randomly generated and real-life cases.