A 14 Bit 1 GS/s Segmented CMOS DAC with Glitch-Free Switching for 5G New Radio Sub-6 GHz Transmitters
2025 International Circuits and Systems Symposium-ICSYS-Annual, Kuala-Lumpur, Malaysia, 24 - 26 November 2025, pp.112-115, (Full Text)
- Publication Type: Conference Paper / Full Text
- Doi Number: 10.1109/icsys65149.2025.11379915
- City: Kuala-Lumpur
- Country: Malaysia
- Page Numbers: pp.112-115
- Istanbul University Affiliated: No
Abstract
This paper presents a 14 bit, 1 GS/s segmented CMOS DAC with a glitch free switching mechanism for 5G New Radio (NR) transmitters. Fabricated in 65 nm CMOS and operating from a 1 V supply, the design combines a 6 bit current steering (CS) MSB section with an 8 bit binary weighted resistive ladder (BWRL) LSB section, achieving an efficient tradeoff between speed and power. A flip-flop based synchronization circuit ensures glitch free transitions and enhances spectral purity. The prototype occupies 0.05 mm(2), consumes 30 mW, and achieves differential nonlinearity (DNL) between -0.17 LSB and +0.15 LSB and integral nonlinearity (INL) from -0.25 LSB to +0.27 LSB. Measured performance shows signal-to-noise ratio (SNDR) of 78 dB and spurious-free dynamic range (SFDR) of 80 dB at 10 MHz, and 72 dB/75 dB at Nyquist, with robustness within +/- 5% across PVT. Benchmarking against recent works, the proposed DAC achieves the highest Schreier figure of merit (177 dB), confirming its suitability for compact, and energy efficient 5G NR sub 6 GHz transmitters.