A New Approach for VDMOSFETs' Gate Oxide Degradation Based on Capacitance and Subthreshold Current Measurements Under Constant Electrical Stress
IEEE TRANSACTIONS ON ELECTRON DEVICES, vol.65, no.4, pp.1650-1652, 2018 (SCI-Expanded, Scopus)
- Publication Type: Article / Article
- Volume: 65 Issue: 4
- Publication Date: 2018
- Doi Number: 10.1109/ted.2018.2808162
- Journal Name: IEEE TRANSACTIONS ON ELECTRON DEVICES
- Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus
- Page Numbers: pp.1650-1652
- Istanbul University Affiliated: Yes
Abstract
In this brief, we proposed a new gate oxide degradation model for vertical double diffused MOS devices under constant electrical stress. To form a complete model, we separated the changes associated with gate oxide and Si-SiO2 interface. We presented oxide trap-induced gate oxide and interface trap-induced Si-SiO2 interface degradation effects on the model, separately. We used capacitance measurements for gate oxide and subthreshold current measurements for Si-SiO2 interface degradation. We presented the survive of the stress-induced gate oxide and interface capacitances during stress time. We also expressed the mathematical expressions for parts of the proposed model.