Ultra low power wide range four quadrant analog multiplier

KELEŞ S., Keles F.

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, vol.102, no.3, pp.491-500, 2020 (SCI-Expanded) identifier identifier

  • Publication Type: Article / Article
  • Volume: 102 Issue: 3
  • Publication Date: 2020
  • Doi Number: 10.1007/s10470-019-01491-1
  • Journal Name: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
  • Journal Indexes: Science Citation Index Expanded (SCI-EXPANDED), Scopus, Aerospace Database, Applied Science & Technology Source, Communication Abstracts, Compendex, Computer & Applied Sciences, INSPEC, Metadex, DIALNET, Civil Engineering Abstracts
  • Page Numbers: pp.491-500
  • Istanbul University Affiliated: Yes

Abstract

A novel four quadrant FGMOS analog multiplier having properties such as low voltage-low power and wide input linearity range is presented. Power consumption of the proposed multiplier is 26.2 nW and the input swing is rail-to-rail which is obtained by choosing the ratio of input capacitances to total capacitance of FGMOS transistors resulting a reduction in the transconductance. Other important features of the proposed multiplier are the bandwidth of 52.5 MHz and maximum THD of 2.04% (when the input voltages are at supply voltage level).